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MC10EL34, MC100EL34 5V ECL /2, /4, /8 Clock Generation Chip
Description
The MC10/100EL34 is a low skew /2, /4, /8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as multiple EL34s in a system. The 100 Series contains temperature compensation.
Features
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16 1 SO-16 D SUFFIX CASE 751B
MARKING DIAGRAMS*
16 10EL34G AWLYWW 1 A WL YY WW G 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package 16 100EL34G AWLYWW
* * * * * * *
50 ps Output-to-Output Skew Synchronous Enable/Disable Master Reset for Synchronization PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V Internal Input 75 kW Pulldown Resistors on CLK(s), EN, and MR Pb-Free Packages are Available*
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
November, 2006 - Rev. 10
1
Publication Order Number: MC10EL34/D
MC10EL34, MC100EL34
VCC 16 EN 15 D Q /2 Q R NC CLK 14 R /4 Q R /8 Q R 13 CLK VBB 12 11 MR 10 VEE 9
Table 1. FUNCTION TABLE
CLK* Z ZZ X EN* L H X MR* L L H Function Divide Hold Q0-3 Reset Q0-3
*Pins will default low when left open. Z = Low-to-High Transition ZZ = High-to-Low Transition
1 Q0
2 Q0
3 VCC
4 Q1
5 Q1
6 VCC
7 Q2
8 Q2
Table 2. PIN DESCRIPTION
Pin CLK, CLK EN MR Q0, Q0 Q1, Q1 Q2, Q2 VBB VCC VEE NC Function ECL Diff Clock Inputs ECL Sync Enable ECL Master Reset ECL Diff /2 Outputs ECL Diff /4 Outputs ECL Diff /8 Outputs Reference Voltage Output Positive Supply Negative Supply No Connect
*All VCC pins are tied together on the die. Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. Logic Diagram and Pinout Assignment
Table 3. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charge Device Model Value 75 KW N/A > 1 KV > 100 V > 2 KV Level 1 Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in 191 Devices
Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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MC10EL34, MC100EL34
Table 4. MAXIMUM RATINGS
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board <2 to 3 sec @ 248C <2 to 3 sec @ 260C SO-16 SO-16 SO-16 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI v VCC VI w VEE Condition 2 Rating 8 -8 6 -6 50 100 0.5 -40 to +85 -65 to +150 130 75 33 to 36 265 265 Unit V V V V mA mA mA C C C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Table 5. 10EL SERIES PECL DC CHARACTERISTICS VCC = 5.0 V; VEE = 0 V (Note 2)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 4) Input HIGH Current Input LOW Current 0.5 3920 3050 3770 3050 3.57 3.0 4010 3200 Min Typ Max 39 4110 3350 4110 3500 3.7 4.6 150 0.5 4020 3050 3870 3050 3.65 3.0 4105 3210 Min 25C Typ Max 39 4190 3370 4190 3520 3.75 4.6 150 0.3 4090 3050 3940 3050 3.69 3.0 4185 3227 Min 85C Typ Max 39 4280 3405 4280 3555 3.81 4.6 150 Unit mA mV mV mV mV V V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.06 V / -0.5 V. 3. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V.
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MC10EL34, MC100EL34
Table 6. 10EL SERIES NECL DC CHARACTERISTICS VCC = 0 V; VEE = -5.0 V (Note 5)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 6) Output LOW Voltage (Note 6) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 7) Input HIGH Current Input LOW Current 0.5 -1080 -1950 -1230 -1950 -1.43 -2.0 -990 -1800 Min Typ Max 39 -890 -1650 -890 -1500 -1.30 -0.4 150 0.5 -980 -1950 -1130 -1950 -1.35 -2.0 -895 -1790 Min 25C Typ Max 39 -810 -1630 -810 -1480 -1.25 -0.4 150 0.3 -910 -1950 -1060 -1950 -1.31 -2.0 -815 -1773 Min 85C Typ Max 39 -720 -1595 -720 -1445 -1.19 -0.4 150 Unit mA mV mV mV mV V V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. VEE can vary +0.06 V / -0.5 V. 6. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V.
Table 7. 100EL SERIES PECL DC CHARACTERISTICS VCC = 5.0 V; VEE = 0 V (Note 8)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 9) Output LOW Voltage (Note 9) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 10) Input HIGH Current Input LOW Current 0.5 3915 3170 3835 3190 3.62 2.2 3995 3305 Min Typ Max 39 4120 3445 4120 3525 3.74 4.6 3975 3190 3835 3190 3.62 2.2 4045 3295 Min 25C Typ Max 39 4120 3380 4120 3525 3.74 4.6 3975 3190 3835 3190 3.62 2.2 4050 3295 Min 85C Typ Max 42 4120 3380 4120 3525 3.74 4.6 Unit mA mV mV mV mV V V
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / -0.5 V. 9. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V.
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MC10EL34, MC100EL34
Table 8. 100EL SERIES NECL DC CHARACTERISTICS VCC = 0 V; VEE = -5.0 V (Note 11)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 12) Output LOW Voltage (Note 12) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 13) Input HIGH Current Input LOW Current 0.5 -1085 -1830 -1165 -1810 -1.38 -2.8 -1005 -1695 Min Typ Max 39 -880 -1555 -880 -1475 -1.26 -0.4 -1025 -1810 -1165 -1810 -1.38 -2.8 -955 -1705 Min 25C Typ Max 39 -880 -1620 -880 -1475 -1.26 -0.4 -1025 -1810 -1165 -1810 -1.38 -2.8 -955 -1705 Min 85C Typ Max 42 -880 -1620 -880 -1475 -1.26 -0.4 Unit mA mV mV mV mV V V
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / -0.5 V. 12. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V.
Table 9. AC CHARACTERISTICS VCC = 5.0 V; VEE = 0.0 V or VCC = 0.0 V; VEE = -5.0 V (Note 14)
-40C Symbol fmax tPLH tPHL tSKEW tJITTER tS tH tRR VPP tr tf Characteristic Maximum Toggle Frequency Propagation Delay to Output CLK to Q0 CLK to Q1,2 MR to Q Min 1.1 960 900 750 100 1.0 400 250 400 150 225 200 1000 475 400 250 400 150 225 200 1000 475 1200 1140 1060 Typ Max Min 1.1 960 900 750 100 1.0 400 250 400 150 225 200 1000 475 1200 1140 1060 25C Typ Max Min 1.1 970 910 790 100 1.0 1210 1150 1090 85C Typ Max Unit GHz ps
Within-Device Skew (Note 15) Cycle-to-Cycle Jitter Setup Time EN Hold Time EN Set/Reset Recovery Input Swing (Note 16) Output Rise/Fall Times Q (20% - 80%)
ps ps ps ps ps mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. 10 Series: VEE can vary +0.06 V / -0.5 V. 100 Series: VEE can vary +0.8 V / -0.5 V. 15. Within-device skew is defined as identical transitions on similar paths through a device. 16. VPPmin is minimum input swing for which AC parameters guaranteed. The device has a DC gain of 40.
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MC10EL34, MC100EL34
There are two distinct functional relationships between the Master Reset and Clock:
Internal Clock Disabled MR CLK Q0 Q1 Q2 EN Internal Clock Enabled
CASE 1: If the MR is de-asserted (H-L), while the Clock is still high, the outputs will follow the first ensuing clock rising edge.
Internal Clock Disabled MR CLK Q0 Q1 Q2 EN Internal Clock Enabled
CASE 2: If the MR is de-asserted (H-L), after the Clock has transitioned low, the outputs will follow the second ensuing clock rising edge. Figure 2. Timing Diagrams
The EN signal will "freeze" the internal divider flip-flops on the first falling edge of CLK after its assertion. The internal divider flip-flops will maintain their state during the freeze. The EN is deasserted (LOW), and after the next falling edge of CLK, then the internal divider flip-flops will "unfreeze" and continue to their next state count with proper phase relationships.
TRR CLOCK CLOCK TRR
MR OUTPUT
MR OUTPUT
CASE 1 Figure 3. Reset Recovery Time
CASE 2
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MC10EL34, MC100EL34
Q Driver Device Q
Zo = 50 W
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device MC10EL34D MC10EL34DG MC10EL34DR2 MC10EL34DR2G MC100EL34D MC100EL34DG MC100EL34DR2 MC100EL34DR2G Package SO-16 SO-16 (Pb-Free) SO-16 SO-16 (Pb-Free) SO-16 SO-16 (Pb-Free) SO-16 SO-16 (Pb-Free) Shipping 48 Units / Rail 48 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel 48 Units / Rail 48 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC10EL34, MC100EL34
PACKAGE DIMENSIONS
SO-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
ECLinPS are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MC10EL34/D

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